This invention relates to a high withstand voltage semiconductor device, and more particularly, to a high withstand voltage semiconductor device having a resistive field plate.
One type of high withstand voltage semiconductor devices has a resistive field plate between a high voltage electrode (e.g., anode) and a low voltage electrode (e.g., cathode) which are commonly formed on the same plane of a substrate.
The resistive field plate is intended to make small current to flow therein upon an application of withstand voltage between the high and low voltage electrodes, so as to relieve a surface electric field formed at the substrate between the high and low voltage electrodes.
FIG. 9 is a plan view showing such a prior art high withstand voltage semiconductor device having the resistive field plate while FIG. 10 is a plan view depicting the resistive field plate used for the high withstand voltage semiconductor device in FIG. 9. FIG. 11 is a cross sectional view taken along the line XI—XI of the high withstand voltage semiconductor device in FIG. 9.
As can be seen in FIG. 11, the device has a silicon oxide insulation (SOI) substrate 53 in which a mono-crystalline silicon substrate 51, an insulation film 52 of silicon oxide, and a high resistance n type substrate 54 are stacked. On an upper surface of the n type substrate 54, a p type anode region 55 and an n type cathode region 56 are selectively formed. On an upper surfaces of the p type node region 55 and the n type cathode region 56, respectively, a p type contact region 58 and an n type contact region 59 both of high impurity concentration are selectively formed.
On the surface of the n type substrate 54 between the p type anode region 55 and the n type cathode region 56, a so-called LOCOS (localized oxidation of silicon) film 60 is formed by means of selective oxidation. On the LOCOS film 60, a vortex planar pattern resistive field plate 61 is formed of polysilicon (see FIG. 10).
As especially can be seen in FIG. 9, the resistive field plate 61 consists of three components, namely, an annular first resistive field plate 611 connected to the anode 62, a second resistive field plate 612 surrounded by the first resistive field plate 611 and connected to the cathode 63, a vortex resistive field plate 61a having one end connected to the resistive field plate 61, and the other end connected to the second resistive field plate 612. In FIG. 11, a reference numeral 64 denotes an interlayer insulation film.
Configured as in FIG. 11, in order to relieve electric field in the surface of the n type substrate 54, or to develop a uniform distribution of the electric field in the surface of the same, a space between the vortex lines (or vortex pitch) should be reduced in the resistive field plate 61a, that is, turns of the vortex should be increased in number.
However, with the reduced space, entry of undesired particles such as dust between the vortex lines during the manufacturing process may cause a short circuit between a pair of the adjacent plates. Thus, the space between vortex lines must be kept a certain distance to avoid the above disadvantage, and this imposes a restriction to the prior art configuration in enhancing withstand voltage.
In contrast, another high withstand voltage semiconductor device is intended to accomplish increased withstand voltage by providing capacitive coupling field plate on the surface of lateral semiconductor device (refer to Japanese Patent Laid-open (Unexamined) Publication No. 2002-353448.
More specifically, the capacitive coupling field plate of this high withstand voltage semiconductor device is of vertical dual stack structure where a lower layer includes a plurality of annular conductive field plates arranged concentric with one another as if they were floating while an upper layer includes annular conductive field plates each occupying an area right above a space between a pair of the adjacent field plates in the lower layers.
Configured in such a manner, application of voltage between an anode and a cathode, formed are capacities between the anode and the conductive field plates in the lower layer, between the conductive field plates in the lower and upper layers, and between the conductive field plates in the lower layer and the cathode. Thus, the anode and the cathode are connected therebetween by couplings of more than one capacities. This enables the substrate to exhibit a uniform distribution of the electric field in its surface.
In the capacitive coupling field plate structure as mentioned above, however, the conductive field plates do not have their respective potentials fixed at specific levels, and accordingly, the withstand voltage adversely varies.
As has been recognized, when the vortex resistive field plate is applied between the anode and cathode, the space between the vortex lines should be greater due to a restriction of the manufacturing, which results in an insufficient withstand voltage. On the other hand, with the capacitive coupling field plates, the conductive field plates respectively assume unstable potentials, which results in a varied withstand voltage.